Routing data buses over long wires, such as on a computer chip, may result in differences in propagation delay between segments of the data bus. Commonly, if the propagation delay over the bus exceeds the clock cycle time, one or more corrective measures must be employed, such as clock manipulation at both the source and destinations of the data (e.g., using an early clock at the source and a late clock at the destination), intermediate sampling (e.g., pipelining) of the data along the path, and/or using a wider data bus at a lower clock frequency. These corrective measures add complexity to the design and/or clocking scheme, reduce performance quality, and/or increase routing congestion. Furthermore, propagation delay does not scale with process technology shrinking.